1024-Bit EEPROM iButton
ELECTRICAL CHARACTERISTICS (continued)
(T A = -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
IO PIN: 1-Wire WRITE
Standard speed
60
120
Write-Zero Low Time
(Notes 2, 16, 17)
t W0L
Overdrive speed, V PUP > 4.5V
5
15.5
μs
Overdrive speed
6
15.5
Write-One Low Time
(Notes 2, 17)
t W1L
Standard speed
Overdrive speed
1
1
15
2
μs
IO PIN: 1-Wire READ
Read Low Time
(Notes 2, 18)
Read Sample Time
(Notes 2, 18)
t RL
t MSR
Standard speed
Overdrive speed
Standard speed
Overdrive speed
5
1
t RL +
t RL +
15 -
2-
15
2
μs
μs
EEPROM
Programming Current
Programming Time
Write/Erase Cycles (Endurance)
(Notes 21, 22)
Data Retention
(Notes 23, 24, 25)
I PROG
t PROG
N CY
t DR
(Notes 5, 19)
(Note 20)
At +25°C
At +85°C (worst case)
At +85°C (worst case)
200k
50k
40
0.8
10
mA
ms
Years
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
Note 17:
Note 18:
Limits are 100% production tested at T A = +25°C and/or T A = +85°C. Limits over the operating temperature range and rel-
evant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
System requirement.
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times.
The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more
heavily loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required.
Maximum value represents the internal parasite capacitance when V PUP is first applied. If a 2.2k Ω resistor is used to pull
up the data line, 2.5μs after V PUP has been applied, the parasite capacitance does not affect normal communications.
Guaranteed by design, characterization, and/or simulation only. Not production tested.
V TL , V TH , and V HY are a function of the internal supply voltage, which is a function of V PUP , R PUP , 1-Wire timing, and
capacitive loading on IO. Lower V PUP , higher R PUP , shorter t REC , and heavier capacitive loading all lead to lower values of
V TL , V TH , and V HY .
Voltage below which, during a falling edge on IO, a logic 0 is detected.
The voltage on IO must be less than or equal to V ILMAX at all times the master is driving IO to a logic 0 level.
Voltage above which, during a rising edge on IO, a logic 1 is detected.
After V TH is crossed during a rising edge on IO, the voltage on IO must drop by at least V HY to be detected as logic 0.
The I-V characteristic is linear for voltages less than 1V.
Applies to a single device attached to a 1-Wire line.
The earliest recognition of a negative edge is possible at t REH after V TH has been reached on the preceding rising edge.
Defines maximum possible bit rate. Equal to t W0LMIN + t RECMIN .
Interval after t RSTL during which a bus master is guaranteed to sample a logic 0 on IO if there is a DS1972 present.
Minimum limit is t PDHMAX ; maximum limit is t PDHMIN + t PDLMIN .
Numbers in bold are not in compliance with legacy 1-Wire product standards. See the Comparison Table.
ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from V IL to V TH . The actual
maximum duration for the master to pull the line low is t W1LMAX + t F - ε and t W0LMAX + t F - ε , respectively.
δ in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from V IL to the input-high
threshold of the bus master. The actual maximum duration for the master to pull the line low is t RLMAX + t F .
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3
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